1. Field of the Invention
The invention relates to binary arithmetic units particularly of the one's complement subtractive variety.
2. Description of the Prior Art
One's complement subtractive addition and subtraction is a commonly utilized arithmetic arrangement in present day general purpose digital computers. For example, the SPERRY UNIVAC 1100 Series computers utilize one's complement subtractive arithmetic units, (SPERRY UNIVAC is a registered trademark of the SPERRY RAND CORPORATION). The one's complement binary number representation has the property that the designation of +zero (+0) and -zero (-0) are different where: EQU +0 = (000 . . . 0).sub.2 EQU -0 = (111 . . . 1).sub.2
In the SPERRY UNIVAC 1100 Series processors, the arithmetic operations of addition and subtraction are performed with one's complement subtractive adders. Such a device utilizes a Boolean subtracter wherein addition is performed by forming the one's complement of one of the operands and subtracting it from the other. Subtraction is performed by subtracting without forming the complement of the number. The one's complement subtractive adder has the property that the value of (-0) can be generated in only two ways: EQU (-0) + (-0) = -0 EQU (-0) - (+0) = -0
One's complement addition and subtraction can also be performed utilizing a Boolean adder. Subtraction is performed by forming the one's complement of one of the operand inputs and adding it to the other. Addition is performed by adding the two operands without forming the complement. With this adder arrangement (-0) is produced only when a number is subtracted from itself or a number and its complement is added as follows: EQU (+x) - (+x) = -0 EQU (+x) + (-x) = -0
A problem arises in implementing a computer having a one's complement subtractive arithmetic unit utilizing commercially procurable LSI components such as ALU chips and microprocessor slices, such LSI components being normally designed utilizing two's complement adders. A two's complement adder is a Boolean adder circuit that performs addition and subtraction by utilizing the two's complement binary number representation. A two's complement adder may be utilized as a one's complement adder by providing an end-around carry from the most significant to the least significant stage. Heretofore, however, it has not been possible to utilize such two's complement adders to perform in the manner of a one's complement subtractive adder.